Many options have been advanced to improve short channel effects or punch through from the drain to the source of a transistor in high speed field effect transistors. Improvements in short channel effects are particularly important in the field of integrated circuit manufacturing as the shortest channel devices limit the speed of the circuit. If the devices can be made shorter and carry more current, they operate faster. The limit to making shorter devices or transistors is the change in threshold voltage that occurs as the distance between the source and drain is reduced.
The use of deep boron implant or "halo" is known for reducing short channel effects. However, such an implant is lightly doped so as to not add capacitance and, hence, decrease switching speeds. Since these implants are not heavily doped, they cannot prevent penetration of the depletion regions of the field effect transistor diffusions into the underlying semiconductor substrate.
In U.S. Pat. No. 4,101,922, issued on Jul. 18, 1978, there is disclosed a doping layer disposed within a semiconductor substrate which overlaps a source electrode of a transistor by a significant distance for controlling the threshold voltage of the transistor with the distance between the channel surface of the transistor and the buried doping layer underneath the gate electrode being critical to the operation of the transistor. Buried doping layers are also disclosed in U.S. Pat. No. 4,506,436, by Paul E. Bakeman, Jr. et al, issued on Mar. 26, 1985 and in U.S. Pat. No. 4,961,165, issued on Oct. 2, 1990. The buried doping layers in these latter two patents are purposely placed deep into the semiconductor substrate so that they do not degrade diffusion capacitance or device substrate sensitivity. In IBM Technical Disclosure Bulletin, Vol. 21, No. 9, February 1979, pages 3823-3825, entitled "Double Polysilicon Dynamic Random-Access Memory Cell With Increased Storage Capacitance" by V. L. Rideout, there is disclosed a self-aligned implant constructed in a double overlapping polysilicon structure for a dynamic random access memory storage cell. The teaching in this article prevents very high levels of doping or doping gradients between the N+ and P+ junctions as a low leakage structure which must support dynamic random access memory node voltages as required in his structure.